In an electronic system, an integrated circuit, such as an FPGA, may interface with an external memory device, such as a synchronized dynamic random access memory (SDRAM). To write data to the SDRAM, the FPGA provides control, address, clock, and data signals to the SDRAM, which uses the clock signals to determine when to sample the data signals in order to store the provided data at the specified address locations. To read data from the SDRAM, the FPGA provides control, address, and clock signals to the SDRAM, which retrieves the stored data from the specified address locations and transmits the retrieved data to the FPGA along with a clock signal that the SDRAM generated from the clock signal provided to it by the FPGA. The FPGA uses the clock signal received from the SDRAM, which is synchronized with the data signals received from the SDRAM, to determine when to sample those data signals for storage and further processing within the FPGA.
During read operations, the clock signal provided by the SDRAM to the FPGA is typically a non-continuous clock (also referred to as a strobe) that lasts only as long as the transmitted burst of retrieved data. For example, in a double data rate (DDR) transfer of data, where each rising and falling edge of the clock signal corresponds to a bit transition in each serial bit stream of retrieved data, the strobe contains a number of clock pulses equal to half the number of data bits in each serial bit stream.
Due to skew resulting from (sometimes indeterminate and/or variable) round-trip delay from the time that the FPGA transmits its clock signal to the SDRAM until the time that the FPGA receives the strobe from the SDRAM, the strobe will typically be asynchronous relative to the FPGA's local reference clock signals.
The non-continuous and asynchronous nature of the clock signal provided by the SDRAM must be taken into consideration when designing an FPGA with the capability of reading data from such an external SDRAM. Providing this capability gets more difficult as clock speeds and data transfer rates increase with newer technology.